CP in chips generally refers to CP tests, also known as Chip tests.
What is CP test
CP test is between Wafer fabrication and packaging in the whole chip manufacturing process. The test object is for every Die in the Wafer. The purpose is to ensure that every Die in the Wafer can basically meet the characteristics or design specifications of the device, usually including verification of voltage, current, timing and function.
The specific operation of CP test is that after the Wafer is made, thousands of bare DIE (unpackaged chip) rules are distributed all over the Wafer. Since the chip packaging has not been carried out, it is only necessary to connect these exposed chip pins with Tester through Probe to carry out chip test, which is CP test.
2. Why do WE need to do CP test
Generally, during the chip packaging stage, some pins will be encapsulated inside the chip, resulting in some functions cannot be tested after packaging, so CP test in Wafer is the most appropriate.
Moreover, after the Wafer is made, due to manufacturing defects caused by process deviation, equipment failure and other reasons, there will be a certain amount of defective products in the bare DIE distributed on the Wafer. The purpose of CP test is to find out the Wafer Sort before packaging, and at the same time, it can avoid the failure to test the chip performance after packaging, optimize the production process, simplify the steps, improve the rate of good products delivered, and reduce the cost of subsequent packaging test.
What CP is in the chip
In addition, some companies will grade the chips based on the results of CP testing and put these products into different markets, so buyers need to be aware of this.
Three, what are the test contents
SCAN is used to check whether the logical functions of chips are correct. During DFT design, ScanChain is inserted into the DesignCompiler first, and Automatic Test Pattern Generation (ATPG) is used to automatically generate SCAN Test vectors. During the SCAN test, SCAN Shift mode is entered first, ATE loads the pattern into the register, and SCAN Capture mode is used to Capture the results. The next time you enter Shift mode, output the results to ATE for comparison.
2, a Boundary SCAN
Boundary SCAN is used to check whether the chip pin function is correct. Similar to SCAN, Boundary SCAN is controlled by inserting Boundary Register between IO pins and using JTAG interface to monitor the input and output status of pins.
Four, what are the test methods
1, DC/AC Test
DC test includes Open/Short test of chip Signal PIN, PowerShort test of power PIN, and test whether the DC current and voltage parameters of the chip meet the design specifications. AC test detects whether the AC signal quality and timing parameters of the chip meet the design specifications.
2, the RF Test
The function and performance of RF are very important for wireless communication chip. CP RF test to detect whether the logic function of RF module is correct.
3. Memory
The number of memory tests is large, because chips are often integrated with various types of memory (such as ROM/RAM/Flash). In order to test the read/write and storage functions of memory, BUILT-IN SelfTest (BIST) logic is usually added In advance during design for memory self-test. The chip enters various BIST functions through special pin configuration. After testing, the BIST module feeds back the test results to Tester.
(1) ROM (Read-Only Memory) Reads data for CRC check to check whether the storage is correct.
(2) In addition to detecting Read/Write and storage functions, some tests also cover DeepSleep's Retention function and Margin Write/Read, etc.
(3) Embedded Flash in addition to the normal reading and writing and storage functions, but also to test the erasing function.
(4) Wafer needs to be subjected to Baking and Stress compression to test whether Flash Retention is normal.
(5) Margin Write/Read, Punch Through tests, etc.
4. Other Function tests
Other chip function test is used to test whether other important chip functions and performance meet design specifications.

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