What are the differences between SMT and traditional chip packaging?

With the development of science and technology, the global chip packaging process is changing from the double-in-line through hole plug type to the surface mount package (SMT) that Kingyu semiconductor will talk about today.
Surface Mounted Technology (SMT) is the most popular Technology and process in electronic assembly industry. Electronic circuit Surface Mount Technology (SMT) is called Surface Mount or Surface Mount Technology. SMC/SMD is a Circuit assembly technology in which a pin or short lead surface assembly component (SMC/SMD in Chinese) is installed on the Printed Circuit Board (PCB) surface or other substrate surface and is welded and assembled by reflow welding or immersion welding.
Different from the traditional packaging form, today's SMT (surface mount technology) is more difficult to chip packaging, more stringent requirements, more stringent technology packaging form, including wafer level packaging (WLP), THREE-DIMENSIONAL packaging (3DP) and system level packaging (SiP) three.
What is Wafer level packaging (WLP)?
Wafer Level Packaging (WLP) is an advanced Packaging technology, which has developed rapidly in recent years due to its advantages of small size, excellent electrical performance, good heat dissipation and low cost.
Unlike traditional packaging, wafer packaging encapsulates the chip while it is still on the wafer. A protective layer can be attached to the top or bottom of the wafer, and then circuits are connected to cut the wafer into individual chips.
What are the differences between SMT and traditional chip packaging?
Compared with traditional packaging, wafer level packaging has the following advantages:
1. Small package size
The lack of wiring, bonding, and plastic processes means that the package does not need to extend out of the chip, making the WLP package size almost equal to the chip size.
2. High transmission speed
Compared to traditional metal lead products, WLP generally has shorter connections and performs well at high performance requirements such as high frequencies.
3. High-density connection
WLP can use array connection, the connection between the chip and the circuit board is not limited to the chip around, improve the connection density per unit area.
4. Short production cycle
In the whole process of WLP from chip manufacturing to packaging to finished products, the intermediate links are greatly reduced, the production efficiency is high, and the cycle is shortened a lot.
5. Low process cost
WLP is packaged and tested at the silicon wafer level to achieve cost minimization through mass production. The cost of WLP depends on the number of qualified chips on each wafer, and the trend towards smaller chip design sizes and larger wafer sizes has resulted in a corresponding reduction in the cost of individual device packages. WLP can make full use of wafer manufacturing facilities and low cost of production facilities.
At present, wafer level packaging technology has been widely used in flash memory, EEPROM, high-speed DRAM, SRAM, LCD drivers, RF devices, logic devices, power/battery management devices and simulator components (voltage regulators, temperature sensors, controllers, operational amplifiers, power amplifiers) and other fields.
What is 3D packaging (3DP)?
3 d package, English abbreviation (3DP), including CIS emitter, MEMS package, standard device package. It refers to the packaging technology of stacking more than two chips vertically in the same packaging body without changing the size of the packaging body, so as to achieve the function and performance of large chips. It originated from NOR/NAND and SDRAM laminated packaging.
The main features include: multi-function, high efficiency; Large capacity, high density, doubling of functions and applications per unit volume and low cost.
What is System-level encapsulation (SiP)?
System package, will be a variety of functions (including CPU, memory, etc.) chip integration in a package, integrated assembly into a multilayer device structure, and can provide a variety of functions of a single standard packaging, form a system or subsystem, in order to achieve higher performance, function and processing speed, at the same time greatly reduce the space requirements of electronic devices inside. To the electronic System level of the so-called Convergent System.
System-level encapsulation has two very important characteristics:
(1) Integrate chips with different processes and functions into one package to achieve powerful system functions;
(2) The discrete components on the previous PCB version are integrated into the multi-layer integration structure to miniaturize the System and achieve the so-called Convergent System.
The main purpose of encapsulation is to realize the connection and protection between the internal and external circuits of the chip. These three more advanced packaging forms have their own strengths and application occasions are different. Although it is not popular at present, it must be the direction of development in the future. Time will tell us which one will become the most mainstream way in the near future.

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