What is the chip packaging process?

Chip packaging is the shell used to install semiconductor integrated circuit chips, which has the function of placing, fixing, sealing, protecting chips and enhancing electric heating performance. Chip packaging is a bridge to communicate the inner world of the chip and the external circuit. The chip contacts are connected to the pins of the package shell with wires, and the pins are connected to other devices through the wires on the printed board. Encapsulation plays an important role in CPU and other LSI integrated circuits. The number of pins increases, the pin spacing decreases, the weight decreases, and the reliability improves, making it easier to use.
ICPackage(IC package form) refers to the chip (Die) and different types of frame (L/F) and plastic seal (EMC) formed by different shapes of seals.
There are many kinds of IC, which can be classified according to the following criteria:
According to packaging materials:
Metal packaging, ceramic packaging, plastic packaging.
Metal packaging is mainly used for military industry or aerospace technology, no commercial products;
Ceramic packaging is better than metal packaging, also used in military products, occupy a small amount of commercial market;
Because of its low cost, simple process and high reliability, plastic packaging is used in consumer electronics;
According to the connection mode with PCB board, it can be divided into:
PTH packaging and SMT packaging.
Pth-pinthroughole, through-hole;
What is the chip packaging process?
At present, most IC on the market are SMT type.
According to the packaging appearance, it can be divided into:
Two key factors determine the form of encapsulation:
Sealing efficiency. Chip area/seal area as close as possible to 1:1;
Pin number. The more pins, the more advanced, but the technical difficulty also increases accordingly;
Among them, CSP is the most advanced technology, using FlipChip technology and bare sheet packaging, chip area/packaging area =1:1;
Qfn-quadflatno-leadpackage Quadrangle pin - free flat package.
Soic-smaloutlineic small appearance IC package.
TSSSOP - ThinSmalShrinkoutlinePackage thin packaging appearance.
Bga-balgridaraypackage Ball grid array package.
Csp-chipscalepackage chip size level package.
Lead frame.
Provide circuit connection and Die fixed function;
The main materials are copper, silver plating, NiPdau and other materials.
L/F has Etch and Stamp two processes;
Easy to oxidize, stored in nitrogen cabinet, humidity is less than 40%RH;
Except FOR BGA and CSP, all other packages adopt LeadFrame, while BGA adopts Substrate;
Weld gold wire.
Realize the electrical physical connection between chip and external lead frame;
The gold thread is made of 99.99% high purity gold;
At the same time, due to cost considerations, copper and aluminum wire technology is currently used. The advantage is to reduce the cost, increase the difficulty of the process, reduce the output;
Wire diameter determines conductable current; 0.8mil, 1.0mil, 1.3mils, 1.5mils and 2.0mils;
MoldCompound plastic seal/epoxy resin.
Main components: epoxy resin and various additives (curing agent, modifier, demoulding agent, dyeing agent, flame retardant, etc.);
The main function is: wrap Die and LeadFrame in molten state, provide physical and electrical protection, prevent external interference;
Storage conditions: -5 ° storage, temperature return 24 hours at room temperature.

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