What is encapsulation? Briefly describe the development process

China has the international advanced level in the field of semiconductor packaging and testing, the volume has entered the top three in the world, and there is no generation difference between technology and world-class level. It is the best one among the three links of integrated circuit, and the development speed is significantly higher than other competitors.
Packaging, IC chip final protection and integration
After a long process, from design to manufacture, finally obtain an IC chip. A chip, however, is so small and thin that it can easily be scratched and damaged without external protection. In addition, because of the small size of the chip, it is not easy to install the circuit board manually without a larger shell. Therefore, encapsulation is described next in this article.
At present, there are two common packages, one is common in electric toys, black shaped like a centipede DIP package, the other is common when buying boxed CPU BGA package. As for other packaging methods, there was the PGA (Pin Grid Array; Pin Grid Array) or a modified VERSION of THE DIP QFP (plastic square flat package). Since there are so many packaging methods, DIP and BGA packaging will be described below.
What is encapsulation? Briefly describe the development processTraditional packaging, enduring
The first is Dual Inline Package; DIP), as can be seen from the figure below, the IC chip with this package looks like a black centipede at the foot of the double row connection, which is impressive. This package method is the earliest ADOPTED IC package technology, with the advantage of low cost, suitable for small chips without too many wires. However, because most of the plastic is used, the heat dissipation effect is poor, can not meet the requirements of the current high-speed chip. As a result, most of the chips in this package are long-lived chips, like OP741 in the picture below, or smaller chips with fewer holes and less speed requirements.
As for the Ball Grid Array (BGA) package, the package size is smaller than the DIP and can be easily fitted into smaller devices. In addition, because the pins are located below the chip, more metal pins can be accommodated than DIP, which is suitable for chips requiring more contacts. However, this packaging method is expensive and the connection method is more complex, so it is mostly used in high-unit products.
Mobile devices rise and new technologies leap onto the scene
However, using these packaging methods requires considerable volume. Such as the current mobile device, wearable device, etc., need quite a variety of components, if each component is packaged independently, combined will consume very large space, so there are currently two methods to meet the requirements of reducing the volume, respectively SoC (System On Chip) and SiP (System In Packet).
In the early days of the smartphone boom, the term SoC could be found in various financial magazines, but what is SoC? In simple terms, it is to integrate the ORIGINAL IC with different functions into a chip. By this method, not only can the size of the chip be reduced, but also the distance between different ics can be reduced, and the calculation speed of the chip can be improved. As for the production method, it is in the IC design stage, put all the different IC together, and then through the design process introduced previously, make a mask.
However, the SoC is not all good. Designing a SoC requires considerable technical coordination. When IC chips are packaged separately, each package has external protection, and the distance between IC and IC is far, so there will be no interactive interference. But when all the ics are packaged together, that’s when the nightmare begins. IC design factory should change from simple design OF IC to understand and integrate all functions of IC, increase the workload of engineers. In addition, there are also many situations where the high frequency signal of the communication chip may affect the IC of other functions.
In addition, the SoC also needs to obtain IP authorization from other vendors to put components designed by others into the SoC. It is necessary to obtain the design details of the whole IC to make a complete optical mask, which also increases the design cost of SoC. One might wonder why not design your own? Because the design of a variety of IC needs a lot of knowledge related to the IC, only like Apple so many gold enterprises, can have the budget to hire top engineers from well-known enterprises to design a new IC, through cooperation authorization or more cost-effective than their own research and development.
Instead, SiP appears
As an alternative, SiP leaps onto the integrated chip stage. Unlike SoC, it buys individual ics and packages them one last time, thus eliminating the IP licensing step and greatly reducing the design cost. In addition, because they are independent ics, the degree of interference with each other is greatly reduced.
The most famous SiP product is the Apple Watch. Because the internal space of Watch is too small to adopt traditional technology, and the design cost of SoC is too high, SiP becomes the first choice. SiP technology can not only reduce the size, but also narrow the distance between each IC, becoming a feasible compromise solution. Here’s the structure of the Apple Watch chip, and you can see quite a bit of IC embedded in it.
After the completion of packaging, it is necessary to enter the testing stage, in this stage to confirm whether the packaging finished IC has normal operation, correct after it can be shipped to the assembly plant, we see the electronic products. At this point, the semiconductor industry will complete the entire production task.

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